Protocol overview

The serial protocol presented here can be used in multiple configurations. 

It is based on a transmission line from the transmitter to the receiver working at high speed. 

It also needs a signal from the receiver to the transmitter to synchronize them. 

Only one occurrence of this signal is necessary between transmitter and receiver even if multiple serial links are implemented (see example below).

 


Figure 1: Interface between TX and RX using multiple serial links

 

14 bits of useful data are transmitted between transmitter and receiver encoded in 16 bits.

 

Figure 2


Figure 2: Frame

 

These 14 bits are first scrambled, and then the overhead is added. The clk bit is a single bit that is toggling and can be used to monitor the synchronization of the interface. The disparity processing is then done on these 15 bits to obtain the 16 bits frame transmitted.

 

These different stages of encoding are realized to cope with the limitation of a serial interface. First, an AC coupled interface between transmitter and receiver implies that the transmission be DC balance, otherwise the AC coupling capacitor will drift and the received data will be corrupted. Then the CDR in the reception stage usually contains a PLL. This means that there must be transitions in the transmission otherwise this PLL will lose its lock. The scrambling, clk bit and disparity processing ensure a deterministic transmission with a DC balance between +/- 16 and a max run length of the transmission of 32.

Note: Current CDR can work with max run length of 80 and above.