Why ESIstream ?

The ESIstream protocol is born from a severe need of the following combination:

•Reduced data overhead on serial links, as low as possible.
•Increased rate of useful data when linking ADCs operating at GSPS speeds with FPGAs on a serial interface.
•Simplified hardware implementation, simple enough to be built on RF SiGe technologies.

An early form of ESIstream has been implemented in EV5AS210, a 5bit 20GSPS demonstrator ADC from e2v.

The protocol has now matured and is being implemented in other devices.

It works on standard FPGA serial I/Os.

ESIstream is particularly useful when just serialising is not sufficient.
When the data overhead must be reduced down to the minimum, 
when the effective data rate must be increased,
when the hardware implementation must be kept as simple and as light as possible,
when any of the above is needed, that is when #ESIstream becomes relevant.