A serial interface protocol for data converters
A serial interface protocol for data converters
The protocol is proposed and maintained by Teledyne-e2v, but it is not proprietary and everyone is free to adopt it to take advantage of its 87.5% data rate efficiency.
The ESIstream protocol is born from a strong need of the following combination:
- Reduce data overhead on serial links.
- Increase rate of useful data when linking high-speed data converters operating at GSPS sampling rate with a FPGA.
- Simplify hardware implementation to be built on RF SiGe technologies.
Learn more about ESIstream by reading the protocol specification and protocol presentation.
ESIstream main benefits
ESIstream main benefits
- Deterministic and low link latency
- Multi-devices synchronization
- Demonstrated lane rate up to 12.8 Gbps
- Multi-lanes synchronization
- Guaranteed DC balance, ±16 bits running disparity
- Sufficient number of transitions with a maximum run length of 32 bits
- Synchronization monitoring
- Receiver (RX) IPs dedicated for EV12AQ600/5 High-speed ADC.
- 32-bit & 64-bit SERDES data path allowing a lane rate up to 12.8 Gbps.
- RX with deterministic latency implementation
- RX uses less logic resources compare to version V2-1.
- RX decoding latency reduced compare to version V2-1.
- Xilinx Kintex Ultrascale KU060 supported
- Xilinx Kintex Ultrascale KU040 supported
- Xilinx Virtex7 7VX690 supported
- Python scripts & Python install environment guide.
- RX IP user guide.
- Transmitter (TX) & Receiver (RX) IPs
- 32-bit & 64-bit SERDES data path allowing a lane rate up to 12.8 Gbps.
- Xilinx Kintex Ultrascale KU040 supported
- Intel Arria 10 GX supported