A serial interface protocol for data converters
The protocol is proposed and maintained by Teledyne-e2v Semiconductors, but it is not proprietary and everyone is free to adopt it to take advantage of its 87.5% data rate efficiency and ease of use.
The ESIstream protocol is born from a strong need of the following combination:
Reduce data overhead on serial links.
Increase rate of useful data when linking high-speed data converters operating at GSps sampling rate with a FPGA.
Simplify hardware implementation to be built on RF SiGe technologies.
Learn more about ESIstream by reading the Protocol specification.
ESIstream 14B/16B main benefits
Deterministic and low link latency
Minimal hardware implementation
Demonstrated lane rate up to 12.8 Gbps
Guaranteed DC balance, ±16 bits running disparity
Maximum run length of 32 bits