NEW IP Packages available

  • Increases lane rate, up to 12.8 Gbps ( tested with EV12AQ600\605 ADC ).
  • Relaxes FPGA timing constraints by reducing frame clock frequency in FPGAs.
  • Supports more diverse range of FPGAs ( Xilinx KU040 and Intel FPGA Arria 10 GX)

ESIstream is an open-source, efficient, high speed serial data interface protocol using CML transceivers, 14b/16b encoding and minimal hardware implementation.

ESIstream simplifies and accelerates design developments.

The protocol is proposed and maintained by Teledyne-e2v, but it is not proprietary and everyone is free to adopt it to take advantage of its 87.5% data rate efficiency.

The ESIstream protocol is born from a strong need of the following combination:

    • Reduce data overhead on serial links.
    • Increase rate of useful data when linking high-speed converters operating at GSPS speeds with FPGAs on a serial interface.
    • Simplify hardware implementation to be built on RF SiGe technologies.

Learn more about ESIstream by reading the protocol specification and protocol presentation.