Different stages of encoding/decoding are implemented to manage the
limitations of a serial interface.
An AC coupled interface requires a DC balance, otherwise the AC coupling
link will tend to drift and the received data will be corrupted.
The Clock Data Recovery (CDR) in the RX transceiver stage, which usually
contains a Phased Locked Loop (PLL), specifies a minimum number of
transitions over a period of time. Otherwise, the PLL can lose its lock.
Scrambling, Clk bit and Disparity processing ensure a deterministic DC
balance transmission between +/- 15 and a maximum run length of 32 Unit
interval (UI).
The run length defines a number of UI without transitions on the serial
lane.