ESIstream Package
XILINX FPGA package V3
Kintex Ultrascale - KU060 - xcku060-ffva1517-1-c
ESIstream TX and RX vhdl design example using XM107 loopback board and XM105 debug board
ESIstream RX vhdl design example dedicated for EV12AQ60x ADC.
SERDES width: 16-bit, 32-bit and 64-bit
Evaluation Kit: ADA-SDEV-KIT2
Vivado: 2019.1
Kintex Ultrascale - KU040 - xcku040-ffva1156-2-e
ESIstream TX and RX vhdl design example using XM107 loopback board
ESIstream RX vhdl design example dedicated for EV12AQ60x ADC.
SERDES width: 16-bit, 32-bit and 64-bit
Evaluation Kit: KCU105
Vivado: 2019.1
Virtex7 - 7VX690 - xc7vx690tffg1761-2
ESIstream TX and RX vhdl design example using XM107 loopback board
ESIstream RX vhdl design example dedicated for EV12AQ60x ADC.
SERDES width: 16-bit, 32-bit and 64-bit
Evaluation Kit: VC709
Vivado: 2019.2
Virtex Ultrascale - VU9P - xcvu9p-flga2104-1-e
ESIstream RX vhdl design example dedicated for EV12AQ60x ADC.
SERDES width: 16-bit, 32-bit and 64-bit
Evaluation Kit: VCU118
Vivado: 2019.2
INTEL FPGA PACKAGE V2-1
Arria 10 GX
ESIstream TX and RX vhdl design example using KAYA FMC loopback board.
ESIstream RX vhdl design example dedicated for EV12AQ60x ADC.
SERDES width: 64-bit
Evaluation Kit: Attila - REFLEX CES
Quartus Prime 18.1
Modelsim 10.5b Intel FPGA edition.
Xilinx FPGA PACKAGE V2-2
Kintex Ultrascale - KU060 - xcku060-ffva1517-1-c
ESIstream RX vhdl design example dedicated for EV12AQ60x ADC.
SERDES width: 32-bit and 64-bit
Evaluation Kit: ADA-SDEV-KIT2
Vivado: 2019.1
Kintex Ultrascale - KU040 - xcku040-ffva1156-2-e
ESIstream TX and RX vhdl design example using XM107 loopback board
ESIstream RX vhdl design example dedicated for EV12AQ60x ADC.
SERDES width: 32-bit and 64-bit
Evaluation Kit: KCU105
Vivado: 2019.1
Virtex7 - 7VX690 - xc7vx690tffg1761-2
ESIstream RX vhdl design example dedicated for EV12AQ60x ADC.
SERDES width: 64-bit
Evaluation Kit: VC709
Vivado: 2019.2