IP Package
IP Package
XILINX FPGA
XILINX FPGA
Kintex Ultrascale KU060
Kintex Ultrascale KU060
- Receiver (RX) IPs dedicated for EV12AQ600/5 High-speed ADC.
- 32-bit & 64-bit SERDES data path allowing a lane rate up to 12.5 Gbps.
- RX with deterministic latency implementation
- RX logic resources utilization optimized
- RX decoding latency optimized.
- Tcl scritps to generate Vivado projects automatically.
- Testbench for simulation.
- FPGA reference: xcku060-ffva1517-1-c
- Evaluation Kit: ADA-SDEV-KIT2 a development platform for space grade FPGA systems.
- Documentation:
- Desing guide & User guide available here.
- Python scripts & Python install environment guide.
- AN2201- Migrate the ESIstream_Xilinx_KU060_V2-2 IP package to KU115
High-speed ADC EV12AQ600 (TX) to Xilinx FPGA KU060 (RX)
Kintex Ultrascale KU040
Kintex Ultrascale KU040
- Receiver (RX) IPs dedicated for EV12AQ600/5 High-speed ADC.
- 32-bit & 64-bit SERDES data path allowing a lane rate up to 12.8 Gbps.
- RX with deterministic latency implementation
- RX uses less logic resources compare to version V2-1.
- RX decoding latency reduced compare to version V2-1.
- Tcl scritps to generate Vivado projects automatically.
- Testbench for simulation.
- FPGA reference: xcku040-ffva1156-2-e
- Evaluation Kit: KCU105
- Documentation: Desing guide & User guide available here.
- Transmitter (TX) & Receiver (RX) IPs available and tested with XM107 FMC loopback board.
- Receiver (RX) IP dedicated for EV12AQ600/5 High-speed ADC.
- 32-bit & 64-bit SERDES data path allowing a lane rate up to 12.8 Gbps.
- Tcl scritps to generate Vivado projects automatically.
- Testbench for simulation.
- FPGA reference: xcku040-ffva1156-2-e
- Evaluation Kit: KCU105
- Documentation: Desing guide & User guide available in the package.
High-speed ADC EV12AQ600 (TX) to Xilinx FPGA KU040 (RX)
KU040 FPGA (TX & RX) loopback using XM107FMC board.
Virtex7 7VX690
Virtex7 7VX690
- Receiver (RX) IPs dedicated for EV12AQ600/5 High-speed ADC.
- 64-bit SERDES data path allowing a lane rate up to 11.3 Gbps for speed grade -2.
- RX logic resources utilization optimized
- RX decoding latency optimized
- Tcl scritps to generate Vivado projects automatically.
- Testbench for simulation.
- FPGA reference: xc7vx690tffg1761-2
- Evaluation Kit: VC709
- Documentation: Desing guide & User guide available here.
- Transmitter (TX) & Receiver (RX) IPs available and tested with two VC709 using four optical fiber cables as physical serial interface. One FPGA is the transmitter the other FPGA is the receiver. The synchronization signal is sent through a SMA cable.
- 16-bit SERDES data path allowing a lane rate up to 6.25 Gbps.
- Tcl scritps to generate Vivado projects automatically.
- Testbench for simulation.
- FPGA reference: xc7vx690tffg1761-2
- Evaluation Kit: VC709
- Documentation: Desing guide & User guide available in the package.
High-speed ADC EV12AQ600 (TX) to Xilinx FPGA 7VX690 (RX)
Virtex7 FPGA (TX) to Virtex7 FPGA (RX)
INTEL FPGA
INTEL FPGA
Arria 10 GX
Arria 10 GX
- Transmitter (TX) & Receiver (RX) IPs available and tested with KAYA FMC loopback test board.
- Receiver (RX) IP dedicated for EV12AQ600/5 High-speed ADC.
- 64-bit SERDES data path allowing a lane rate up to 10.3125 Gbps.
- Full Quartus 18.1 projects (vhdl sources, IPs, constraint file).
- Testbench for simulation using Modelsim 10.5b Intel FPGA edition.
- FPGA: Intel FPGA Arria 10 GX.
- Evaluation Kit: Attila Arria 10 GX FMC evaluation kit from REFLEX CES
- Documentation: Desing guide & User guide available in the package.
High-speed ADC EV12AQ600 (TX) to Intel FPGA Arria 10 GX (RX)
Arria 10 GX FPGA (TX & RX) loopback using KAYA FMC board.