The Disparity Bit ensures deterministically the advantages brought
statistically by the scrambling process.
Even with scrambling process, a large running disparity can still occur
with very low probability and could produce excessive eye shifts. These
eye shifts could be balanced by a more complicated equalization stage in
the receiver if the running disparity was still limited. However, a PRBS
does not bind the running disparity deterministically, thus the data could
be corrupted on the reception end and it could eventually cause the PLL in
the CDR to lose its lock. The implementation of the Disparity Bit process
prevents from this eventuality.
The transmitter constantly monitors the disparity of the transmission.
For each frame, the running disparity is calculated and 2 cases can occur:
-
The running disparity of the transmission
does not increase above ±16 (+16 and -16 included). In
this case, the disparity bit is set to ‘0’ and the 15 bits composed of
the scrambled data and of the Clk Bit are transmitted as such.
-
The running disparity of the transmission does increase
above ±16 (+16 and -16 excluded). In this case, the 15 bits composed of
the scrambled data and of the Clk Bit are inverted and the disparity bit
is set to '1'.
The running disparity is updated with the disparity of the frame. See
Annex C for an example.
The disparity bit ensures that the longest possible series of ’1’ or ‘0’
transmitted is of 48 bits and the Clk Bit reduces the effective value to
32.
The disparity bit also ensures that the running disparity does not exceed
± 16 (included) which satisfies the DC balance condition.
In normal operating mode, the receiver will check the disparity bit first.
If it is high then it will invert the received data and descramble them.
Otherwise it will only descramble them. From this point the data are
available for processing.
