A serial interface protocol for data converters
The protocol is proposed and maintained by Teledyne-e2v, but it is not proprietary and everyone is free to adopt it to take advantage of its 87.5% data rate efficiency.
The ESIstream protocol is born from a strong need of the following combination:
- Reduce data overhead on serial links.
- Increase rate of useful data when linking high-speed data converters operating at GSPS sampling rate with a FPGA.
- Simplify hardware implementation to be built on RF SiGe technologies.
Learn more about ESIstream by reading the protocol specification and protocol presentation.
ESIstream main benefits
- Deterministic latency
- Multi-devices synchronization
- Demonstrated lane rate up to 12.8 Gbps
- Multi-lanes synchronization
- Guaranteed DC balance, ±16 bits running disparity
- Sufficient number of transitions with a maximum run length of 32 bits
- Synchronization monitoring
New IP Package available
- Supports more diverse range of FPGAs with Xilinx Kintex Ultrascale KU040 and Intel Arria 10 GX
- Lane rate up to 12.8 Gbps ( tested with EV12AQ600\605 ADC ).
- Relaxes FPGA timing constraints by reducing frame clock frequency in FPGAs.