AN01 - Migrate ESIstream package to any Xilinx Kintex Ultrascale FPGA reference.
This application note aims at explaining how to migrate ADA-SDEV-KIT2 ESIstream package (Xilinx KU060 FPGA), to any reference of the Xilinx Kintex Ultrascale FPGA family.
Unzip the package in your work directory.
Rename the package folder. For this application note we select the FPGA reference xcku115-flvd1517-2-e.
Open one of the TCL script (see FAQ-07 to select the right TCL script depending on your needs)
For this application note we select script_64_dl.tcl.
Change the FPGA reference variable fpga_ref
"set fpga_ref xcku060-ffva1517-1-c" to "set fpga_ref xcku115-ffvd1517-2-e"
Change the package reference variable package_reference
"set package reference xilinx_ku060" to "set package reference xilinx_ku115"
Open the testbench.
Change log output file path to:
"file_open(fstatus, logfile, "c:\vw\xilinx_ku115\tb_log.txt", append_mode);"
Open the build.py python script.
Change the package reference variable package_reference:
"package_reference = xilinx_ku060" to "package reference = xilinx_ku115"
Open Vivado 2019.1 and launch the modified TCL script.
Tools > Run Tcl Script…
Browse and select the TCL script and click OK.
It takes few minutes to generate the project.
At the end of the project generation, the project closes.
Select the project in the Recent Projects view and open it.
For each Xilinx IP in Project MANAGER > Sources > IP Sources tab.
Right click on the IP
Upgrade IP
OK
OK
Generate (Generate Output Products)
Open and configure the clk_wiz_0 IP according to the new FPGA board schematic.
clk_wiz_0 IP generates a 100 MHz system clock output from a 200 MHz clock input in ADA-SDEV-KIT2 ESIstream package project. The 100 MHz system clock is used by UART wrapper, registers map modules and GT system clock.
If your design use a different clock input IO standard and frequency, then change the IP configuration.
Update the new clock period and the IO standard in the xdc constraint file rx_esistream_64b.xdc.
Open and configure the gth_8lanes_64b IP according to the new FPGA board schematic, High-Speed Serial Lanes (HSSLs) and reference clock (SSO) mapping.
For this application note we select quad X0Y3 (127) , quad X0Y2 (126) and MGTREFCLK0 of quad X0Y2 as reference clock for the two quads.
Update the GTH HSSLs and SSO PACKAGE_PIN in the rx_esistream_64b.xdc constraints file.
The gth_8lanes_64b.xdc file located in "C:\vw\xilinx_ku115\vivado_rx_aq600_64b\vivado_rx_aq600_64b.srcs\sources_1\ip\gth_8lanes_64b\synth\" helps to identify FPGA package pin according to the GTH lane index [0:7].
Update all top file, rx_esistream_top.vhd, entity signals PACKAGE_PIN value in the rx_esistream_64b.xdc constraints file according to the new board schematic.
At this stage you can generate the FPGA Bitstream.
At this stage you can also simulate the design using vivado simulator clicking on Run Simulation.
Before running the simulation, check that the testbench high speed clock (clk_bit) half period value is set according to the GTH transceiver lane rate configuration (40 ps for a lane rate of 12.5 Gbps) in tb_pkg.vhd file.
Run the simulation for 6.33 µs minimum to start receiving samples from the ESIstream RX in ramp test mode.