ESIstream protocol is born from a severe need of the following combination:

• Increase rate of useful data, when linking data converters operating at GSps speeds with FPGAs on a serial interface, reducing data overhead on serial links, as low as possible.

• Simplified hardware implementation, simple enough to be built on RF SiGe technologies.

ESIstream provides an efficient High-Speed serial interface based on a 14B/16B encoding using a Linear Feedback Shift Register (LFSR) scrambling unit, a Disparity Bit (DB) to ensure deterministic DC balance transmission and a toggling bit, the Clk Bit (CB), to enable synchronization monitoring.

It is license-free and supports in particular serial communication between FPGAs and High-Speed data converters.

However, ESIstream can be used in any system requiring a serial interface. For instance, between two FPGAs or two ASICs.

An ESIstream system is made up of the following elements.

• A transmitter (TX) can be an ADC or any Logic Devices (LD) such as a FPGA or an ASIC.

• A receiver (RX) can be a DAC or any Logic Devices such as a FPGA or an ASIC.

• A number of serial lanes (L ≥ 1) to transmit serial data.

• A synchronization signal (sync) used to initialize the communication and synchronize the transmitter and receiver. On a single device, only one occurrence of the SYNC signal is necessary between the transmitter and the receiver even if multiple serial links are implemented.

There is no clock lane in a serial interface. For each lane, the receiver should recover the clock from the data.

Different stages of encoding/decoding are implemented to manage the limitations of a serial interface.

An AC coupled interface requires a DC balance, otherwise the AC coupling link will tend to drift and the received data will be corrupted.

The Clock Data Recovery (CDR) in the RX transceiver stage, which usually contains a Phased Locked Loop (PLL), specifies a minimum number of transitions over a period of time. Otherwise, the PLL can lose its lock.

Scrambling, Clk bit and Disparity processing ensure a deterministic DC balance transmission between +/- 15 and a maximum run length of 32 Unit interval (UI).

The run length defines a number of UI without transitions on the serial lane.

An ESIstream frame is 16-bit wide. The frame is transmitted, LSB first, between the transmitter and the receiver.

ESIstream uses a 14B/16B encoding, 14-bit of useful data are scrambled and then 2-bit of overhead are concatenated to create the 16-bit ESIstream frame.

The overhead is composed of:

• The Clk Bit (CB), which is toggling between each consecutive frame sent through a single serial lane. The Clk bit can be used to monitor the synchronization of a single lane.

• The Disparity Bit (DB), which is the result of a calculation, the disparity processing, done on the 14-bit data and on the Clk Bit.

These different stages of encoding are realized to manage the limitations of a serial interface. First, an AC coupled interface between transmitter and receiver implies that the transmission be DC balance, otherwise the AC coupling capacitor will drift and the received data will be corrupted. Secondly the CDR in the reception stage usually contains a PLL. This means that there must be transitions in the transmission otherwise this PLL will lose its lock.

The scrambling, clk bit and disparity processing ensure a deterministic transmission with a DC balance between +/- 15 and a max run length of the transmission of 32.

Note: Current CDR can work with max run length of 80 and above.

Scrambling ensures a statistical DC balanced transmission. It also statistically ensures that there are transitions in the transmission.

ESIstream uses an additive scrambling to avoid error propagation in case of a single bit error. The Linear Feedback Shift Register (LSFR), which generates a Pseudo Random Binary Sequence (PRBS), is based on a Fibonacci architecture and uses the polynomial X¹⁷+X³+1. It has a length of 2¹⁷ - 1. See Annex A for more information.

Instead of using a shift of one bit per operation, it uses shifts of 14 bits per operation to adapt to the size of the data being scrambled.

The ESIstream LFSR is characterized by the following equations:

Scrambled data (14-bit) are encoded into a 16-bit frame adding two overhead bits, the Clk Bit (CB) and the Disparity Bit (DB).

On each serial lane, the Clk Bit (CB) toggles at every ESIstream frame sent through one serial lane.

The receiver uses the Clk Bit to monitor the link synchronization. If the receiver does not detect that the Clk Bit is toggling properly, then it can state that the link is not synchronous or has lost its synchronization and restart the synchronization process.

The Disparity Bit ensures deterministically the advantages brought statistically by the scrambling process.

Even with scrambling process, a large running disparity can still occur with very low probability and could produce excessive eye shifts. These eye shifts could be balanced by a more complicated equalization stage in the receiver if the running disparity was still limited. However, a PRBS does not bind the running disparity deterministically, thus the data could be corrupted on the reception end and it could eventually cause the PLL in the CDR to lose its lock. The implementation of the Disparity Bit process prevents from this eventuality.

The transmitter constantly monitors the disparity of the transmission.

For each frame, the running disparity is calculated and 2 cases can occur:

• The running disparity of the transmission does not increase above ±16 (+16 and -16 included). In this case, the disparity bit is set to ‘0’ and the 15 bits composed of the scrambled data and of the Clk Bit are transmitted as such.

• The running disparity of the transmission does increase above ±16 (+16 and -16 excluded). In this case, the 15 bits composed of the scrambled data and of the Clk Bit are inverted and the disparity bit is set to ‘1’.

The running disparity is updated with the disparity of the frame. See Annex C for an example.

The disparity bit ensures that the longest possible series of ’1’ or ‘0’ transmitted is of 48 bits and the Clk Bit reduces the effective value to 32.

The disparity bit also ensures that the running disparity does not exceed ± 16 (included) which satisfies the DC balance condition.

In normal operating mode, the receiver will check the disparity bit first. If it is high then it will invert the received data and descramble them. Otherwise it will only descramble them. From this point the data are available for processing.

Each serial lane must be synchronized to align the frames between the transmitter and the receiver and to synchronize the reception scrambler with the transmission scrambler.

The synchronization is controlled through the synchronization (SYNC) signal sent to the receiver and to the transmitter.

The receiver must receive the SYNC signal prior to receive the ESIstream Synchronization Sequence (ESS).

The transmitter generates the ESS when receiving the SYNC signal. The length of the SYNC pulse should be at least as long as one ESIstream frame period (16-bit).

The ESS is composed of two parts:

• The Frame Alignment Sequence (FAS), 32 frames alternating between 0xFF00 and 0x00FF. This sequence bypasses the scrambling, the Clk Bit and the Disparity Bit processing (the sequence is DC balanced). This alignment pattern (COMMA or FLASH pattern) is used by the receiver to align its data on the transmitter output data.

• The PRBS Alignment Sequence (PAS), 32 additional frames containing the scrambling PRBS alone. These frames contain 14 bits of the PRBS plus the Clk Bit and the Disparity Bit. These frames go through the disparity processing, as the PRBS value will start to impact the running disparity of the transmission.