ESIstream provides an efficient High-Speed serial interface based on a 62B/64B encoding using a Linear Feedback Shift Register (LFSR) scrambling unit, a Disparity Bit (DB) to ensure deterministic DC balance transmission and a toggling bit, the Clk Bit (CB), to enable synchronization monitoring.

It is license-free and supports in particular serial communication between FPGAs and High-Speed data converters.

However, ESIstream can be used in any system requiring a serial interface. For instance, between two FPGAs or two ASICs.

An ESIstream system is made up of the following elements.

• A transmitter (TX) can be an ADC or any Logic Devices (LD) such as a FPGA or an ASIC.

• A receiver (RX) can be a DAC or any Logic Devices such as a FPGA or an ASIC.

• A number of serial lanes (L ≥ 1) to transmit serial data.

• A synchronization signal (sync) used to initialize the communication and synchronize the transmitter and receiver. On a single device, only one occurrence of the SYNC signal is necessary between the transmitter and the receiver even if multiple serial links are implemented.

There is no clock lane in a serial interface. For each lane, the receiver should recover the clock from the data.

Different stages of encoding/decoding are implemented to manage the limitations of a serial interface.

An AC coupled interface requires a DC balance, otherwise the link will tend to drift and the received data will be corrupted.

The Clock Data Recovery (CDR) in the RX transceiver stage, which usually contains a Phased Locked Loop (PLL), specifies a minimum number of transitions over a period of time. Otherwise, the PLL can lose its lock.

An ESIstream 62B/64B frame is 64-bit wide. The frame is transmitted, LSB first, between the transmitter and the receiver.

62-bit of useful data are scrambled and then 2-bit of header are concatenated to create a 64-bit ESIstream frame.

The header is composed of:

• The Clk Bit (CB), which is toggling between each consecutive frame sent through a single serial lane. The Clk bit can be used to monitor the synchronization of a single lane. The Clk bit can be disabled and set to 1 to limit the maximum run length to 64.

• The Disparity Bit (DB), which is the result of a calculation, the disparity processing, done on the 62-bit data and on the Clk Bit.

These different stages of encoding are realized to manage the limitations of a serial interface. First, an AC coupled interface between a transmitter and a receiver implies a DC balanced transmission, otherwise the AC coupling capacitor will drift and the received data will be corrupted. Secondly the CDR in the reception stage usually contains a PLL. This means that there must be transitions in the transmission otherwise this PLL will lose its lock.

• When the Clk bit is toggling, the scrambling, the clk bit and the disparity processing ensure a deterministic transmission with a DC balance between +/- 64 and a max run length of the transmission of 128.

• When the Clk bit is set to 1, the scrambling, the clk bit and the disparity processing ensure a deterministic transmission with a DC balance between +/- 64 and a max run length of the transmission of 64.

Note: Current CDR can work with max run length of 80 and above.

Scrambling ensures a statistical DC balanced transmission. It also statistically ensures that there are transitions in the transmission.

ESIstream 62B64B uses an additive scrambling to avoid error propagation in case of a single bit error. The Linear Feedback Shift Register (LSFR), which generates a Pseudo Random Binary Sequence (PRBS), is based on a Fibonacci architecture and uses the polynomial X³¹+X²⁸+1. It has a length of 2³¹ - 1. See Annex A for more information.

Instead of using a shift of one bit per operation, it uses shifts of 14 bits per operation to adapt to the size of the data being scrambled.

The ESIstream LFSR is characterized by the following equations:

Scrambled data (62-bit) are encoded are encoded into a 64-bit frame adding two header bits, the Clk Bit (CB) and the Disparity Bit (DB).

On each serial lane, the Clk Bit (CB) toggles at every ESIstream frame sent through one serial lane.

The receiver uses the Clk Bit to monitor the link synchronization. If the receiver does not detect that the Clk Bit is toggling properly, then it can state that the link is not synchronous or has lost its synchronization and restart the synchronization process.

The Disparity Bit ensures deterministically the advantages brought statistically by the scrambling process.

Even with scrambling process, a large running disparity can still occur with very low probability and could produce excessive eye shifts. These eye shifts could be balanced by a more complicated equalization stage in the receiver if the running disparity was still limited. However, a PRBS does not bind the running disparity deterministically, thus the data could be corrupted on the reception end and it could eventually cause the PLL in the CDR to lose its lock. The implementation of the Disparity Bit process prevents from this eventuality.

The transmitter constantly monitors the disparity of the transmission.

For each frame, the running disparity is calculated and 2 cases can occur:

• The running disparity of the transmission does not increase above ±64 (+64 and -64 included). In this case, the disparity bit is set to ‘0’ and the 63 bits composed of the scrambled data and of the Clk Bit are transmitted as is.

• The running disparity of the transmission does increase above ±64 (+64 and -64 excluded). In this case, the 63 bits composed of the scrambled data and of the Clk Bit are inverted and the disparity bit is set to ‘1’.

In normal operating mode, the receiver will check the disparity bit first.

If the disparity bit is high then the received data are inverted (including the clk bit), then the data are descrambled.

If the disparity bit is low then data are descrambled only.

Each serial lane must be synchronized to align the frames between the transmitter and the receiver and to synchronize the reception scrambler with the transmission scrambler.

The synchronization is controlled through the synchronization signal (SYNC) sent to the receiver and to the transmitter.

The receiver must receive the SYNC signal prior to receive the ESIstream 62B64B Synchronization Sequence (ESS).

The transmitter generates the ESS when receiving the SYNC signal. The length of the SYNC pulse should be at least as long as 32 UI.

The ESS is composed of two parts:

• The Frame Alignment Sequence (FAS) is composed of 32 frames of a 64-bit programmable COMMA, 0x00FFFF0000FFFF00 or 0xACF0FF00FFFF0000. This sequence bypasses the scrambling, the Clk Bit and the Disparity Bit processing (the sequence is DC balanced). This alignment pattern (COMMA or FLASH pattern) is used by the receiver to align its data on the transmitter output data.

• The PRBS Alignment Sequence (PAS), 32 additional frames containing the scrambling PRBS alone. These frames contain 62 bits of the PRBS plus the Clk Bit and the Disparity Bit. These frames go through the disparity processing, as the PRBS value will start to impact the running disparity of the transmission.

The receiver will detect the transition from the FAS to the PAS. The PRBS is reset by the transmitter when receiving the SYNC to avoid the first frame of the PRBS initialization being the COMMA; this to ensure that passive detection is precise to the frame.

The receiver will determine its PRBS initial value after receiving 1 valid frame of the PAS. After that, the synchronization of the link is complete.