ESIstream 14B/16B Package

• ESIstream TX and RX design example using XM107 loopback board

• ESIstream RX design example using EV12AQ600-FMC-EVM rev 2 ADC devkit

Contact Teledyne-e2v support at GRE-HOTLINE-BDC@Teledyne.com for compatibility with EV12AQ600-FMC-EVM rev 1  ADC devkit as it does not support VADJ = 1.5V by default.

• SERDES width: 64-bit

• Evaluation Kit: VCK190

• Vivado: 2021.1

• ESIstream TX and RX design example using XM107 loopback board and XM105 debug board

• ESIstream RX design example using EV12AQ600-FMC-EVM ADC devkit

• SERDES width: 16-bit, 32-bit and 64-bit 

• Evaluation Kit: ADA-SDEV-KIT2 

• Vivado: 2019.1

• User guide: 

  • ESIstream Xilinx package V3

  • Get started with ADA-SDEV-KIT2

• App Note: Migrate to any Xilinx Kintex Ultrascale FPGA reference.

• ESIstream TX and RX design example using XM107 loopback board

• ESIstream RX design example using EV12AQ600-FMC-EVM ADC devkit

• SERDES width: 16-bit, 32-bit and 64-bit 

• Evaluation Kit: KCU105

• Vivado: 2019.1

• User guide: ESIstream Xilinx package V3

• ESIstream TX and RX design example using XM107 loopback board

• ESIstream RX design example using EV12AQ600-FMC-EVM ADC devkit

• SERDES width: 16-bit, 32-bit and 64-bit 

• Evaluation Kit: VC709

• Vivado: 2019.2

• User guide: ESIstream Xilinx package V3

• ESIstream RX design example using EV12AQ600-FMC-EVM ADC devkit

• SERDES width: 16-bit, 32-bit and 64-bit

• Evaluation Kit: VCU118

• Vivado: 2019.2

• ESIstream TX and RX vhdl design example using KAYA FMC loopback board.

• ESIstream RX vhdl design example dedicated for EV12AQ60x ADC.

• SERDES width: 64-bit 

• Evaluation Kit: Attila - REFLEX CES

• Quartus Prime 18.1 

• Modelsim 10.5b Intel FPGA edition.

• User guide: Get started with Arria 10 GX package